In the proposed ramp-rate control strategy, a compensation power will be added with the PV panel DC power to control the ramp-rate of the PV inverter output within a desired level at any instant of time. The basic concept of the ramp-rate control strategy is explained in Fig. 7.2.

Fig. 7.2. Conceptual schematic of the proposed ramp-rate control strategy.

Based on Fig. 7.2, the PV inverter output PINV can be obtained from the PV panel DC power PDC and the compensation power PCOMP using the following expression.

_{DC} _{COMP}

INV

INV *P* *P*

*P* (7.2)

In Fig. 7.2 and (7.2), INV is the inverter efficiency. Taking the time derivative of (7.2) at both sides, the ramp-rate of PINV can now be related with the ramp-rate of PCOMP

and PDC, as given in (7.3).

*dt*

*dP*
*dt*
*dP*
*dt*

*dP* _{DC} _{COMP}

INV

INV (7.3)

where,
*dt*

*dP*_{INV} is the PV inverter output ramp-rate,
*dt*

*dP*_{DC} is the PV panel DC power

output ramp-rate, and
*dt*

*dP*_{COMP} is the compensation power ramp-rate.

To control the rate of the PV inverter output within a desired level, the ramp-rate of PCOMP can be controlled using the expression derived from (7.3), as given below.

*dt*

*dP*
*dt*

*dP*
*dt*

*dP*

*des*
INV DC
INV

INV

COMP 1

(7.4)

where,
*dt* *des*

*dP*_{INV}

is the desired ramp-rate of the PV inverter. If the desired ramp-rate of the inverter output is set to zero, then PV inverter output will not be allowed to change at all. For smoothing purpose, the desired ramp-rate is set to a small negative value during a ramp-down event of the PV module output, and to a small positive value during a ramp-up event of the PV module output as described later.

The expression given in (7.4) is the basic control equation that will be followed to control the ramp-rate of PV inverter output. However, the following modifications are made to accommodate practical situations.

(a) To allow for the slow variations of PDC with the progress of the day, a dead-band function ‘f’ is incorporated with (7.4) that will force the ramp-rate of PDC to be zero if it is within an acceptable limit, defined using the desired ramp-rate of PINV, as shown below.

otherwise ,

if 0

DC

INV DC

INV DC

*dt*

*dP* *dt*

*dP*
*dt*

*,* *dP*

*dt*

*f* *dP* ^{des}

(7.5)

(b) Observing (7.4) it is apparent that when the ramp-rate of PDC is zero, considering the dead-band function mentioned in modification (a), the ramp-rate of PCOMP will be governed by the desired ramp-rate of PINV. However, when the ramp-rate of PDC is zero, then if PCOMP has already attained such a level that removal of PCOMP itself would not create an unacceptable fluctuation in PINV, then it will not be necessary to change PCOMP

for the ramp-rate control. Therefore, the ramp-rate of PCOMP can be made zero during this situation. To accommodate this, a switching function S, as given below, is incorporated with (7.4).

otherwise 1,

0 and

if

0 _{COMP} ^{INV} ^{DC}

*dt*
*f* *dP*
*dt*

*P* *dP*

*S* *,* * _{des}* (7.6)

The modified control equation incorporating the dead-band function ‘f’ and the switching function ‘S’ can be described using the expression below.

*dt*

*f* *dP*
*dt*

*S* *dP*
*dt*

*dP*

*des*
INV DC
INV

INV

COMP 1

^{ (7.7) }

The inverter efficiency INV will depend on the power output of the inverter. The efficiency curve for a given inverter over a range of operating power can be obtained from the manufacturer or developed through testing. As the desired PINV at any given instant is known, INV at the desired PINV can be taken from the efficiency curve and can be used in (7.7) to control the ramp-rate of PCOMP at the necessary level.

Considering a discrete time representation, the ramp-rate of PDC at the k-th instant can be determined using the expression below.

1

DC 1

DC DC

*k*
*t*
*k*
*t*

*k*
*P*
*k*
*k* *P*

*dt*

*dP* (7.8)

where, t(k) is the time at the k-th instant.

The value of the switching function is also incorporated with PCOMP* to force it to zero *
when the conditions of S = 0 are satisfied, as given in (7.6). PCOMP at the k-th instant can
be obtained using (7.9).

_{COMP} _{}^{} _{COMP} 1 ^{COMP} *k* *t* *k* *t* *k*1_{}^{}

*dt*
*k* *dP*

*P*
*S*
*k*

*P* (7.9)

To illustrate the proposed ramp-rate control strategy, a fictitious PV output fluctuation shown in Fig. 7.3(a) is used, where the PV panel output decreases at a ramp-rate of PVRR1 kW/sec from time t1 to t2, remains constant at the level reached at time t2

up to time t3, and again increases from time t3 to time t4 at a ramp-rate of PVRR2

kW/sec. After reaching time t4, the PV output remains constant. To control the
ramp-rate of PINV, (7.7) and (7.9) are used to produce the appropriate amount of PCOMP. The
desired ramp-rate of PINV is defined as the Maximum Allowable Ramp-rate (MARR) in
W/sec. To apply the proposed strategy to any size of PV plant, the ramp-rate units can
also be defined in % of the rated PV capacity/sec. Before time t1, *P*DC remains at a
stable state. Therefore, the ramp-rate of PCOMP is zero according to (7.7), and remains
*zero. From time t*1 to t2, PDC sharply decreases with a ramp-rate of PVRR1. During this
time the ramp-rate of PCOMP is determined using PVRR1 and MARR. At time t2, PVRR1

becomes zero, but PCOMP is not zero yet. Therefore, the ramp-rate of PCOMP from time t2

to t3 is determined using MARR only. From time t3 to t4, PDC sharply increases with a
ramp-rate of PVRR2. During this time, PCOMP is controlled with a ramp-rate determined
using PVRR2 and MARR. After time t4, PVRR2 becomes zero, however, PCOMP is not
*zero yet. Therefore, from time t*4 *P*COMP is controlled using MARR only. At time t5,
*P*COMP becomes zero and the ramp-rate of PDC is also zero. Therefore, the ramp-rate of
*P*COMP is zero after t5 which keeps PCOMP at zero.

Fig. 7.3. An illustration of the proposed ramp-rate control strategy. (a) A hypothetical PV output fluctuation. (b) PV inverter output with appropriately controlled PCOMP to limit the PINV ramp-rate within a desired level.

For moving average control, PCOMP at a given k-th instant depends on the previous values of PDC within the averaging window, w, as given below.

*k*
*w* *P*

*i*
*k*
*P*
*k*

*P*

*w*

*i*

DC 1

0 DC

COMP

###

^{}

(7.10)

Therefore, if moving average is applied to control the ramp-rate of the fluctuation
shown in Fig. 7.3(a), then PCOMP at t>t1 will actually depend on the PDC values before
*t*1. It will not directly depend on the required PCOMP to control the ramp-rate at a desired
level. According to (7.10), PCOMP is only controllable using the length of the averaging
window *w. The higher the number w is chosen, the more is the smoothing effect. *

However, if a high w is chosen for improving fluctuation mitigation performance at the
*k-th instant, it not only impacts the P*COMP at the k-th instant, but also at all the future
time instants. For example, if w is increased by w to increase the smoothing effect at
the *k-th instant, then at any future (k+j)-th instant, the deviation of P*COMP due to the
increase of wi.e.,w) will be,

*P*DC(kW) *P*INV(kW)

*w*
*i*
*j*
*k*
*P*
*w*

*w*

*i*
*j*
*k*
*P*
*j*

*k*
*P*

*w*

*i*
*w*

*w*

*i*

###

###

^{}

1

0 DC 1

0 DC

COMP (7.11)

The deviation PCOMP at the (k+j)-th instant is solely due to the increase of w at the k-th instant. For a given w, k-this deviation will remain in effect for all future time instants even if it is not necessary because of acceptable variations in PDC.

In contrast, according to the proposed ramp-rate control strategy, the amount of
*P*COMP to control the ramp-rate at a given k-th instant can be governed by the desired
ramp-rate of PINV for the k-th instant only and it does not impact the future ramp-rates.

According to (7.9), PCOMP at the k-th time instant is,

###

_{}

*des*

*dt* *k*
*k* *dP*

*P*
*S*
*k*

*P*_{COMP} _{COMP} 1 ^{INV} (7.12)

In (7.12), () denotes a function that determines the ramp-rate of PCOMP for obtaining the desired ramp-rate of PINV at the given ramp-rate of PDC. The value of () is obtained using (7.7). As the proposed strategy does not have a memory effect, PCOMP can be changed at each instant dynamically based on the requirement. This advantage is used in this thesis to improve the fluctuation mitigation performance.

**7.3.2 ** **Improvement of the Fluctuation Mitigation Performance*** *

For a given PV output fluctuation, the duration of the ramping event is inversely proportional to the ramp-rate of the PV output, because the higher the ramp-rate, the faster the PV output changes from one stable state to another stable state. As the time duration for a high-rate ramping event is very short, the amount of energy needed to be used for ramp-rate control is small. Therefore, during the ramping event, the MARR can be reduced in an inverse proportion to the PV panel output ramp-rate (PVRR) to improve the fluctuation mitigation performance without discharging a significant amount of storage capacity. Such an inverse characteristic is given in (7.13) and shown in Fig. 7.4(a).

lim

lim

RR PVRR

PVRR if

RR PVRR

if , PVRR

MARR *,* *k*

*k*

*k*
*k*

*k*

(7.13)

Fig. 7.4. Ramping event dependent selection of MARR. (a) During the ramping event. (b) After the ramping event. (c) Application of MARR and MARR (d) The effect of and MARR versus SoC droop on ramp-rate control.

In (7.13), MARR is the inverse characteristic based desired ramp-rate, to be applied during the ramping event and is a factor to control the degree of inverse characteristic;

RRlim is a threshold of ramp-rate of PDC beyond which the inverse characteristic is
applied. RRlim should be set to a value higher than the ramp-rate of slow variations of
*P*DC to allow PINV to vary with the progress of the day. Once the ramping event is over,
the *P*COMP can be brought to zero with an MARR determined using a SoC droop
characteristic as given by (7.14) and shown in Fig. 7.4(b).

###

###

UB max

UB LB

LB SoC

MARR min

LB min

SoC SoC

if , MARR

SoC SoC

SoC if

, SoC SoC

MARR

SoC SoC

if , MARR

MARR

*k*

*k*
*DB* *k*

*DB*
*k*

*k* (7.14)

In (7.14), MARR is a SoC droop based desired ramp-rate, to be applied once the

ramping event is over; DBMARR and DBSoC are the dead-bands of MARR and SoC, respectively; SoCLB and SoCUB are the lower and upper bands of SoC, respectively, and

|SoC(k)| is the absolute value of the deviation between SoC(k-1) and a user defined reference SoCref. Using the absolute deviation makes the droop characteristic applicable for change of SoC in either direction.

Fig. 7.4(c) identifies the ramping events in a real PV output fluctuation and shows the event driven application of MARRand MARRto control the ramp-rates. SoCLB

defines the amount of energy available for controlling the ramp-rate at MARRmin before entering the droop characteristic. Therefore, SoCLB should be set to a value that represents a sufficient amount of energy to control the ramp-rate at MARRmin (during the worst-case fluctuation) for a certain amount of time that allows for any back up power to come online or any sensitive load to be shut down safely. SoCUB should be set up to a value that represents a substantial portion of the energy needed to control the ramp-rate (during the worst-case fluctuation) before exceeding the saturation limit of the droop characteristic (MARRmax).

The effect of the parameter in (7.13) and the parameters MARRmin and MARRmax in
(7.14) on the fluctuation mitigation performance is shown in Fig. 7.4(d) using a
fictitious PV fluctuation containing a ramping event E1 (time t1 to t2) at a ramp-rate
PVRR, followed by a low PV event E2 (time t2 to t3). During the event E1, MARR is
applicable which is determined by . If = 1, MARR is in direct inverse relation with
the ramp-rate of PDC. If < 1, the degree of the inverse characteristic increases, and
therefore, *P*INV is improved compared to = 1. However, this will be performed at the
expense of additional energy discharged from the storage device as shown in Fig. 7.4(d)
using the shaded region. If > 1, the degree of the inverse characteristic decreases, and
therefore, PINV is reduced compared to = 1, but at the same time a smaller amount of
energy is discharged from the storage device, as shown in Fig. 7.4(d). Although for high
ramp-rate events, the variation of storage energy discharge is not significant, it provides
the user a control over the fluctuation mitigation performance of the proposed strategy.

During the event E2, *P*COMP slowly decreases at MARR determined from the SoC
droop characteristic in (7.14). For a given fluctuation, MARRmin is selected as MARR

so that PINV can be reduced at the same ramp-rate as it reduces during event E1, which

provides a smooth transition in ramp-rate control from event E1 to E2. However, if

|SoC| is higher than SoCLB, then MARR is increased and therefore, PINV reduces at a higher ramp-rate as shown in Fig. 7.4(d). MARRmax in (7.14) needs to be set to a value that allows for the slow variations of PDC, as mentioned for selecting RRlim in (7.13).

The discussions presented above provide only basic guidelines for selection of the control parameters for the proposed strategy. In general, these parameters are user defined and can vary depending on the scenario.

**7.3.3 ** **Energy Utilization for the Control of Ramp-rate **

The amount of energy to be utilised by an energy storage device for controlling the ramp-rate will mainly depend on the PV panel output power, PDC, just prior to start of the fluctuation, and the maximum allowable ramp-rate, MARR. A relation of the energy usage for ramp-rate control to the rated output of a PV panel is established and discussed below using Fig. 7.5. To consider a worst case fluctuation, a PV output power having a sudden fall from the rated value of PDC-rated to zero at time t1is shown in Fig.

7.5(a). In this case it is assumed that PDC does not return to its previous value due to a likely phenomenon of a sustained cloudy period, after time t1. According to the proposed strategy, the PV inverter output will be slowly reduced at the maximum allowable ramp-rate MARR and will become zero at time t2, instead of suddenly dropping to zero. The value of MARR will be determined depending on the situation as shown in Fig. 7.4.

Fig. 7.5. Energy utilization in the proposed ramp-rate control strategy. (a) During negative ramp-rate control. (b) During positive ramp-rate control.

The energy to be discharged by the storage device in controlling the ramp-rate is shown in Fig. 7.5(a) using a shaded area. A similar type of worst case scenario for

positive ramp-rate is shown in Fig. 7.5(b), where the PV output suddenly increases from
*zero to P*DC-rated at time t1. In this case, the positive ramp-rate of the PINV is controlled by
charging the energy storage with certain amount of energy, as indicated using a shaped
area in Fig. 7.5(b). The energy utilised for ramp-rate control, ERRC (Wh) can be derived
using the expression given below.

3600

MARR

1 DC-RRC

###

*N**tot*

*i*

*rated* *i*
*P*

*E* (7.15a)

where, N*tot* is the total number of time-steps between time t1 (seconds) and t2 (seconds),
which can be determined using,

MARR

DC *rated*
*tot*

*N* *P* ^{} (7.15b)

In (7.15a), 3600 is used to bring the unit to kWh, as the calculations are being performed in per second unit. A plot of the ERRC for rated PV capacities up to 5 kW is derived using (7.15) for different values of MARR and is shown in Fig. 7.6. Increase of energy utilization for ramp-rate control with increase in PV capacity and decrease in MARR is observed in Fig. 7.6.

Instead of using PDC-rated, *P*DC(k) can be used in (7.15) to determine the energy
required to control the ramp-rate from the present value of PDC. The amount of energy
determined in this way can be identified as an Energy Buffer (EBuff) to approximately
check the minimum amount of capacity need to be present in the storage to control the
ramp-rate according to the proposed strategy.

Fig. 7.6. Variations of the energy utilization for ramp-rate control with different rated PV output at different MARR.

1 W/sec 2.5 W/sec 5 W/sec

**7.3.4 ** **The Flow Chart of the Proposed Control Strategy **

The flowchart of the proposed ramp-rate control strategy for a given k-th time instant
is shown in Fig. 7.7. The ramp-rate of PDC at the k-th instant PVRR(k) is calculated
using (7.8), and based on this MARRis calculated using (7.13). If PVRR(k) is equal to
or higher than MARRS is set to 1 and the ramp-rate of PCOMP is determined using
(7.7) and in this case the desired ramp-rate is replaced with MARR If PVRR(k) is
found lower than MARR, then a test is performed to find if removal of PCOMP would
create an unacceptable fluctuation in PINV. If ‘Yes’, then S is set to 1 and the ramp-rate
of *P*COMP is determined using (7.7), but in this case the desired ramp-rate is replaced
with MARRdetermined from (7.14). If ‘No’, then the ramp-rate of PCOMP is
determined using (7.7) with S = 0. The ramp-rate of PCOMP(k) is applied to determine
*P*COMP(k) using (7.9). With the value of PCOMP(k) obtained, the present level of SoC is
checked. If it is found within the lower (SoCLL) and upper (SoCUL) limits of SoC,
obtained using the Maximum Depth of Discharge (DoDmax), the Maximum State of
Charge (SoCmax), and buffer energy EBuff, then a charge/discharge operation is
performed depending on the sign of PCOMP(k). According to the proposed strategy, a
*+ve sign means discharge, and –ve sign means charge. Once the discharging/charging *
decision for the time instant is made and the storage is put into operation, the control
system proceeds with a transition into the next time instant.

Fig. 7.7. Flow chart of the proposed ramp-rate control strategy.

Although this thesis has mainly concentrated on the application of battery energy storage, the fundamental idea of ramp-rate control proposed in this thesis would be applicable for other type of energy storage (such as ultra-capacitor).

**7.3.5 ** **Dynamic Model of PV-Storage Integrated System **

The development of a dynamic model is necessary to understand the performance of the proposed strategy in the context of practical system components that are subject to physical device time lags. Detailed switching models of the power electronic converters are used in power-electronics based investigations where sub-cycle phenomena are of interest. However, for the scope of the investigations of this thesis, such fast dynamics are not of interest. Therefore, a simplistic dynamic model of the PV-storage integrated system is developed, as shown in Fig. 7.8, that represents the time-lag related to the associated devices and components. The dynamic model consists of four states which are the PI controller output (y1), the storage power output (y2), storage power output measurement signal (y3), and the PV inverter output (y4). The state equations are given below.

_{2} _{3} _{COMP}_{-}_{ref} _{3}

meas

1 1

*y*
*P*

*K*
*y*
*T* *y*

*dt* *K*
*dy*

*I*

*P*

(7.16a)

_{1} _{2}

sto

2 1

*y*
*T* *y*

*dt*

*dy* (7.16b)

_{2} _{3}

meas

3 1

*y*
*T* *y*

*dt*

*dy* (7.16c)

_{inv} _{DC} _{2} _{4}

inv

4 1

*y*
*y*
*T* *P*

*dt*

*dy* (7.16d)

where, *P*COMP-ref is the reference to the PI controller; Tinv is the inverter time constant;

*T*sto is the storage time constant; Tmeas is the storage output measurement circuit time
delay; K*P** and K**I** proportional and integral gain of the PI controller. *

Fig. 7.8. A dynamic model of the PV-storage integrated system to consider the effect of physical device time-lags.

inv inv

s
1 *T*

s sto

1 1

*T*
s

*P* *I*

*K* *K*

s meas

1 1

*T*